The present invention relates in general to interface circuits providing communication between computer systems and in particular to an interface system permitting a bus master connected to one computer bus to lock another bus and directly read or write access the address space of the other bus.
In some applications, several computer processors are interconnected so that they may communicate with each other as when one computer processor generates data for use by another. Some systems connect the computer processors to the same parallel computer bus and allow them to arbitrate for mastery of the bus thereby to access the same main memory. For example, one processor on a bus may generate data defining a graphics display and store that data in a memory on the bus. A display controller on the bus may from time-to-time read the data out of the memory and update a display accordingly.
Some bus systems permit a bus master to "lock" a bus to prevent another bus master from gaining control. For example, the processor generating display data may first read a data value out of the memory, modify it in some way, and then write the result back into memory. To quickly perform such a read/modify/write operation without interruption to its control of the bus, the processor may lock the bus. A processor may also wish to lock the bus in order to transfer a large block of data without interruption.
However, when various computer processors normally employ differing types of parallel buses, it is not possible to directly connect the computer processors to the same bus. In such case, the processors operate within separate computer systems utilizing separate buses and accessing separate local memories. Typically, each computer system includes one or more ports connected to its bus. The ports of the separate computers can be interconnected so that when a first computer reads data out of its local memory and writes the data to its port, that port signals a port of a second computer that it has data to transfer. The port of the second computer then signals a computer processor within the second computer that incoming data is available. The second computer processor can obtain the data via the second computer port and store the data in its local memory. However, the process of transferring data from a memory location on the first bus to a memory location on the second bus is slow because it requires several bus cycles and ties up processors in both systems. Also, the port-to-port interconnection is not able to make use of bus locking to speed up read/modify/write and block transfer operations.